Leakage power modeling and reduction with data retention

Abstract

In this paper, we study leakage power reduction using power gating in the form of the virtual power/ground rails clamp (VRC) and multi-threshold CMOS (MTCMOS) techniques. We apply power gating to two circuit types: memory-based units and datapath components. Using a microarchitecture-level power simulator, as well as power and timing models derived from detailed circuit designs, we further study leakage power modeling and reduction at the system level for modern high-performance VLIW processors. We show that the leakage power can be over 40% of the total power for such processors. Moreover, we propose time-out scheduling of the VRC to reduce power up to 85.65% for an L2 cache. This power saving results in close to 1/3 of the total power dissipation for the VLIW processors we studied.