Leakage optimization of ultra-shallow junctions formed by solid phase epitaxial regrowth

Abstract

Ultra-shallow p+ junctions formed by solid phase epitaxial regrowth (SPER) have promise for sub-65 nm CMOS technologies. Due to above-equilibrium solid solubilities and minimal diffusion, such junctions can far outperform spike-annealed junctions in terms of resistance, abruptness, and depth. However, the low-temperature annealing does not dissolve the end of range defects creating concerns for junction leakage in the device. In this work, we show how SPER junctions can be optimized to meet the ITRS junction profile and low-power leakage requirements of the 45 nm CMOS node [International Technology Roadmap for Semiconductors (Semiconductor Industry Association, San Jose, CA, 2001)]. Diode leakage is shown to decrease with Ge amorphization depth and B dose and energy. Leakage is shown to increase dramatically with the background doping level. Increasing the regrowth, or post-annealing, thermal budget improves leakage and can be optimized to avoid deactivation. The inclusion of a preanneal does not affect the junction leakage, however co-implanting F increases leakage. The influence of each is explained using various physical and electrical characterization techniques. Optimizing these parameters gives a junction of 9 nm with an Rs of 698 Ω/sq and area leakage of 1E-6 A/cm2 with HALO doping.