Leakage energy estimates for HPC applications

Abstract

Large-scale high-performance systems are energy constrained. With thousands of processing cores at their disposal, these machines contain large amounts of on-chip caches. With a trend of decreasing thresholds in transistors, the amount of leakage current and energy losses has increased dramatically. Coupling the two trends, on-chip caches are responsible for a large portion of total leakage energy losses. In this work, we quantify the on-chip leakage energy losses across a wide set of applications. Our scheme profiles applications to measure cache accesses in order to estimate energy consumption across various levels of caches. Our study indicates that the leakage energy is the dominant form of energy dissipation in on-chip caches and may account for up to 80% of total cache energy, and this trend is expected to increase with every new generation of semiconductor process. Our results also suggest that compiler optimizations have a very limited effect on the total energy consumption of the caches and irrespective of the compiler optimizations, the problem of leakage in caches cannot be effectively addressed by software techniques but requires intervention at circuit and architectural levels. The problem of leakage in caches cannot be neglected in attacking the energy barrier to building exascale systems.