Abstract
A new last-level cache replacement policy for systems with a phase-change memory (PCM) main memory is presented. The proposed policy aims at reducing the write traffic to PCM by considering the fine-grained dirtiness of cache blocks when making a replacement decision. Experimental results show that the proposed policy reduces the write traffic to the PCM by 26 and 17% on average and up to 52 and 33% compared to not recently used and re-reference interval prediction, respectively.
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