Abstract
A new last-level cache replacement policy for systems with a phase-change memory (PCM) main memory is presented. The proposed policy aims at reducing the write traffic to PCM by considering the fine-grained dirtiness of cache blocks when making a replacement decision. Experimental results show that the proposed policy reduces the write traffic to the PCM by 26 and 17% on average and up to 52 and 33% compared to not recently used and re-reference interval prediction, respectively.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
