LC-VCO design optimization at 1/f 2 phase noise performance in 65 nm CMOS technology

Abstract

A way of analytical calculation in the phase noise modeling of the LC-VCO topology without tail current resource is proposed. The noise current imported by the MOS channel is modeled to give approximate evaluation, and the period of the transistor noise is included in the model. Phase noise introduced by the tank loss resistance is also modeled to evaluate the circuit phase noise performance. The circuit has been implemented in a 65 nm CMOS technology. The chip occupies 951 × 705 um2 areas with the buffer and pads. The test result indicates that the VCO core consumes 1.125 mW with a 1.2 V power supply, the frequency of the VCO baseband is from 1.258 to 1.37 GHz, and the multiband frequency is from 0.86 to 1.37 GHz. The best performance of the LC-VCO shows a phase noise of ?129.57 dBc/Hz at 1 MHz offset frequency from a 1.3 GHz carrier, resulting in an excellent FoM of ?191.27 dBc/Hz.