Comparison of proposed source degeneration and conventional D-latch without tail current source QVCO in 0.18 µm CMOS technology

Abstract

This paper presents theoretical analysis of the maximum operating frequency of proposed Source Degeneration (SD) and Conventional D-flip flops are estimated. The approach is based on the voltage transfer function, which is derived from small signal model of the circuit. Design approach with pre and post layout simulation results have been presented in detail and compared the performance in terms of power consumption, self oscillation frequency, sensitivity and supply voltage. With example shows the, all pMOS Voltage Controlled Oscilaator (VCO) with MOS capacitor switched capacitor array (SCA) generates the high frequency sinewave reference signals fed in to both divider for to get quadrature (Q) sinewave signals. Various optimization techniques are implemented while designing a QVCO, which facilitates is used to achieve a low power low phase noise performance. Compared to other types of QVCO, the conventional QVCO shows good phase noise performance than normally achieved 6 dB phase noise improvement with carrier frequency. The simulated results shows about 5 dB, 4 dB, 4 dB and 4 dB of phase noise improvement at 10 kHz, 100 kHz, 1 MHz and 3 MHz offset frequency from the 2.4 GHz carrier frequency. This combinational topology doesn't consume additional power and area than others and shows with improved phase noise performance.