Layout exploration for three-dimensional Networks-on-Chip: Chemical equilibrium simulation approach

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This study presents a heterogeneous layout approach for three-dimensional Networks-on-Chip (3D-NoCs) based on the idea of chemical equilibrium movement principle to optimize the chip area and the wiring length. In order to evaluate the performance of this layout, a hybrid optimization approach named chemical equilibrium simulation algorithm, combining chemical reaction optimization and simulated annealing algorithms, is used to search the optimal solution together with B*-tree as the coding layout. In addition, based on the metropolis criterion of simulated annealing algorithm, the decomposition or the synthesis of chemical reaction is also applied to avoid getting into the local optimum which is provided double guarantee, and thus offers quality solutions. The proposed approach is tested over the simulator of VNoC3 and compared with the state-of-the-art techniques of the literature. The simulation results indicate that, compared with conventional algorithms, the proposed approach efficiently reduces the communication latency and improves the robustness of latency in the sacrificial time range. Moreover, the proposed hybrid optimization strategy is employed in which the better quality solutions can be established compared with its counterparts.