Layout driven logic synthesis system

Abstract

In a system level or logic level design process, the decisions made during early phases of the high level design have the greatest impacts on the performance of the final chip. However, these impacts will not be realised until very late in the physical design stage. In addition, it has been observed repeatedly that the most frustrating problem in IC design is to understand the relationship between the early phase decisions and the final layout result. It is therefore important, in logic synthesis to optimise a cost function which could relate the logic equation and the final layout performance. The authors develop a logic synthesis approach which relies on an accurate design evaluation program to estimate the final design attributes such as layout area and speed. Given a candidate design implementation, an evaluation program will be called upon to provide quick and accurate estimates of the layout area or critical path delay. This information will then be used as a feedback to the logic optimisation system. Based on this feedback, the system will 'reorient' itself toward a new direction for optimisation. Such a scheme represents a more realistic way of generating optimal layout implementations.