Abstract
Silicon-on-insulator technologies are well suited for high temperature circuit design, due to low leakage currents. The reduction of leakage currents is especially important in large repetitive structures such as memories. This paper describes the layout development of a high temperature SRAM cell in a SOI Technology. First, the differences between SOI technologies and standard CMOS processes are presented. It is then discussed, how SOI specific circuit element behavior affects the layout design of different parts of the SRAM cell. Solutions for SOI specific problems are presented and advantages and disadvantages of SOI technologies in static random access memory design are shown.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Facta universitatis - series: Electronics and Energetics
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
