Layout Arrangement Concern for Lateral DMOS With Large Geometric Array Used as Output Device

Abstract

In this paper, the layout arrangement concern for the lateral double-diffused metal-oxide-semiconductor (LDMOS) device with a large geometric array used as the output device has been investigated. Three phenomena have been discovered according to the experimental results: 1) both the cell splicing arrangements and guard ring arrangements can affect the specific on-resistance; 2) the cell splicing arrangements have no effect on the electrostatic discharge (ESD) robustness of both floating gate LDMOS and grounded gate LDMOS; and 3) the guard ring arrangements exhibit a great impact on the ESD robustness of floating gate LDMOS while having no impact on that of the grounded gate LDMOS. In order to understand these phenomena, the Technology Computer Aided design simulations and failure analyses have been carried out. As a result, two different ESD failure mechanisms for the floating gate LDMOS and grounded gate LDMOS are proposed. For floating gate LDMOS, the nonuniform surface electric-field distribution caused by different gate coupling voltage leads to the failure beside the guard ring pad. For grounded gate LDMOS, the nonuniform NPN transistor trigger leads to large current crowding and the failure is beside the gate cluster pad. Furthermore, it is found that there is a contradictory relationship between the specific on-resistance and ESD robustness for the LDMOS. Finally, an optimal layout arrangement has been proposed, which can trade off the specific on-resistance and ESD robustness simultaneously.