Layer assignment for VLSI interconnect delay minimization: M.J. Ciesielski (Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst. MA, USA IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA). vol. 8, no. 6, p. 702–707 (June 1989)

Abstract

A new formulation of the layer assignment problem for VLSI circuits is presented. The objective of this problem is to minimize the interconnect delay by taking into account the resistance and ca- pacitance of interconnect wires and contacts. For MOS circuits with two layers of interconnections the problem is shown to be equivalent to that of minimizing a weighted resistance of the corresponding RC network. This new formulation readily handles wires with preassigned layers, such as power supply lines or module terminals. With user- defined weights assigned to selected nets, this method can be used to minimize critical path delays. The problem is shown to be NP-com- plete. A polynomial time approximation algorithm, based on graph partitioning technique, is presented along with some experimental re- sults.