Lateral tunneling transistors fabricated by plane-dependent Si-doping in nonplanar epitaxy on GaAs (311)A and (411)A substrates

Abstract

We have demonstrated the lateral tunneling transistors on GaAs (311)A and (411)A patterned substrates by using the plane-dependent Si-doping technique. Lateral p +-n + tunneling junctions are formed by growing heavily Si-doped layers on patterned substrates. Current—voltage curves for both transistors show gate-controlled negative differential resistance characteristics. Furthermore, the peak current density of the lateral tunneling diodes fabricated on the (311)A patterned substrates increases as buffer layer thickness is increased, and a typical peak current density of 58 A/cm 2 for p = 6 × 10 19 cm −3 and n = 7 × 10 18 cm −3 is obtained when the buffer layer thickness is 1.2 μm. This study shows that plane-dependent Si-doping in non-planar epitaxy is a promising technique for fabricating tunneling transistors.