(Invited) Recent Progress in Vertical Si/III-V Tunnel FETs: From Fundamentals to Current-Boosting Technology

Abstract

Inherent issue for low-power LSI is lowering supply voltage of transistor while beating physical limit of subthreshold slope (SS = 2.3 k BT/q = 60 mV/dec) [1]. Otherwise, this limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented [2-4]. The steep-slope transistors such as tunnel FETs (TFETs) and impact ionization FETs have therefore been proposed to overcome the limitation and to reduce supply voltage to sub-0.5 V in future LSI. The tunneling transistors are most promising switching devices because of possibility for lower SS than 60 mV/dec. and better compatibility with conventional integration process. However, there are some difficulties in decreasing SS while increasing tunneling current as high as that of conventional FETs. Recently, we reported on new tunnel junction based on III-V/Si interface [4,5] which is formed by selective-area growth of III-V nanowires (NWs) on Si [6-8], and demonstrated vertical TFETs with steeper SS [9,10]. This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials. Here we report on recent progress in the vertical TFETs using III-V NW/Si heterojunction and discuss some current-boosting technology such as strain and other technique. As for integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as InAs and In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping [4,5]. Thus, we integrated InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [8]. Sn was used for n-type dopant, and Zn-pulse doping technique [10] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-ling in this case). The vertical TFET with a single vertically aligned n+-InGaAs/Zn-pulse doped InGaAs axial NW on a p-Si substrate was firstly demonstrated. The device process was reported elsewhere [4,5]. The channel length was 200 nm. In the TFET using the bare InGaAs NW, the tunneling current under revise bias was modulated by gate bias with SS of 80 – 90 mV/dec, and the ION was 2.7 nA/µm at VDS = 0.50 V. With decreasing VDS, the SS become steeper than 60 mV/dec. at low drain current region. The minimum SS was around 50 mV/dec. at VDS= 0.10 V. As for current boosting technology, channel length scaling was characterized [5]. The ION was 100 times enhanced with decreasing the channel length to 50 nm, and the SS decreased to 30 mV/dec. at VDS = 0.10 V. This indicated that the drain end should be close to the tunnel junction width. Next, strain effect was characterized by using InGaAs/InP core-shell nanowire structure. Switching behavior with a SS of 42 mV/dec was obtained under reverse bias direction. This switching characterization appeared at as low as VDS of 10 mV. The SS of the TFET exhibits steeper SS behavior under various VDS. The ION for InGaAs/InP core-shell NW/Si TFET was 10 times higher than that of the bare InGaAs NW/Si TFET. The benefit of InP shell layer is improvement of SS and enhancement of ION. The InP shell layer act as passivation effect on the semiconductor/oxide interface. TEM analysis revealed the large compressive strain was induced at the near InGaAs NW/Si, which ascribes that the uniaxial compressive strain decrease effective band gap of InGaAs/Si while enhancing tunneling probability. Reduction in effective band gap of tunnel junction can partly enhance the tunneling current, but the tunneling leakage at source/channel region was increased degrading SS. Thus, further additional technology to enhance the tunneling current will be discussed.