Abstract
High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. Conventional HLS techniques usually focus on uniform-width resources according to the worst-case data requirements, that is, the largest word length. HLS techniques have been reviewed for the last few years to benefit from multiple word-length fixed point description of the algorithms to be implemented. Aims were to save design area and power consumption. Unfortunately, data-width timing issues over the operation's latency have not been taken into account accurately. In this paper, an HLS process that takes care of the delay of the operators according to the data width is presented. Experimental results show that our approach achieves significant design latency saving or area decrease compared to a conventional synthesis.
Highlights
Multimedia, communications, and, more generally, consumer electronics applications are witnessing a rapid development towards integrating a complex system on a chip (SoC)
Fixed point DSP algorithm implementation based on highlevel synthesis mainly consists of two steps: word-length allocation and high-level synthesis
Provided designs may be optimized, but the overall complexity is reduced. We address such design approaches, and we focus on multiple word-length High-level synthesis (HLS)
Summary
Multimedia, communications, and, more generally, consumer electronics applications are witnessing a rapid development towards integrating a complex system on a chip (SoC). The increasingly demanding requirements for digital signal processing applications (like multimedia, new generations of wireless systems, etc.) lead to the implementation of more and more complex algorithms and systems. To handle this increase in complexity and the time-to-market pressure, design methodologies based on high-level synthesis (HLS) are nowadays required [1,2,3]. An HLS process that takes into account operators with variable latency is proposed It makes it possible to save computation clock cycles, that is, to reduce the design latency when the synthesis is constrained by the number of resources.
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