Abstract
Simultaneous measurements of drain and gate currents in short-channel accumulation-mode SOI p-MOSFET'MOs demonstrate that a latch mechanism may occur in these devices and induce an anomalous behavior of the hot-electron gate current: distortion of I/sub g/(V/sub g/) curves, hysteresis and excessively high gate current values. 2-D MEDICI simulations based on the lucky-electron model qualitatively reproduce the measurements in the latch regime, and explain the unusual gate current dependence on drain and gate biases. The results are of relevance for reliability and modeling issues.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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