LaSiO x - and Al2O3-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

Abstract

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula>/metal gate (HKMG) stacks at a reduced thermal budget (&#x003C;525 &#x00B0;C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of &#x201C;defect decoupling&#x201D; layers&#x2013;LaSiO_<i>x</i> for nMOS and Al₂O₃ for pMOS&#x2013;at the interface between SiO₂ and HfO₂ as a promising approach to engineer the high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiO_<i>x</i> and Al₂O₃ insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiO_<i>x</i> and Al₂O₃ insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al₂O₃) or even improved carrier mobility (LaSiO_<i>x</i>) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al₂O₃ layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiO_<i>x</i> (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiO_<i>x</i> layer on top of the beneficial Al₂O₃ layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle.