Large-scale SRAM-based IP lookup architectures using compact trie search structures

Abstract

SRAM-based pipelined architectures for high-speed IP lookup using Field Programmable Gate Arrays (FPGAs) has recently attracted a great deal of attention from researchers. Due to the limited amount of on-chip memory and the number of I/O pins of FPGAs, compact data structures providing high memory efficiency are in great demand.In IP lookup, a binary trie that is an ordered tree data structure is used to store the routing table entries. In this paper, we propose two compact trie structures denoted Compact Trie Forest (CTF) and Compact Trie∊ (CT∊) for Internet Protocol (IP) lookup. The large variant in node sizes leading to the memory inefficiency in hardware implementation is resolved by using multiple disjoint pipelines in CTF. CT∊ solves the problem within a single pipeline by splitting large nodes into sequentially connected multiple small and fixed size nodes. To support each data structure, two pipelined SRAM-based architectures optimized by allowing multiple memory banks in each stage are also proposed.