Compact trie forest: Scalable architecture for IP lookup on FPGAs

Abstract

Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. Among all existing implementation platforms, Field Programmable Gate Array (FPGA) is a prevailing platform to implement SRAM-based pipelined architectures for high-speed IP lookup because of its abundant parallelism and other desirable features. However, due to the available on-chip memory and the number of I/O pins of FPGAs, state-of-the-art designs cannot support large routing tables consisting of over 350K prefixes in backbone routers. We propose a search algorithm and data structure denoted Compact Trie (CT) for IP lookup. Our algorithm demonstrates a substantial reduction in the memory footprint compared with the state-of-the-art solutions. A parallel architecture on FPGAs, named Compact Trie Forest (CTF), is introduced to support the data structure. Along with pipelining techniques, our optimized architecture also employs multiple memory banks in each stage to further reduce memory and resource redundancy. Implementation on a state-of-the-art FPGA device shows that the proposed architecture can support large routing tables consisting up to 703K IPv4 or 418K IPv6 prefixes. The post place-and-route result shows that our architecture can sustain a throughput of 420 million lookups per second (MLPS), or 135 Gbps for the minimum packet size of 40 Bytes. The result surpasses the worst-case 150 MLPS required by the standardized 100GbE line cards.