Abstract
Switched-current elliptic decimators and interpolators based on bilinear-transformed low-sensitivity ladder structures are proposed. The combination of polyphase networks and doubly terminated ladder structures preserve low passband sensitivity and maximizes time for settling by operating at the lower sampling frequency. The decimators are derived via a z-domain multirate transformation procedure. Two different types of decimator architectures, finite-impulse response (FIR)-infinite-impulse response (IIR) cascade (FIC) and multiple feed-in (MFI) are presented and compared. The complementary IIR-FIR cascade (IFC) and multiple feed-out (MFO) interpolator structures are obtained by direct transposition, which avoids the need for redesign. A third-order elliptic low pass filter is used as prototype for deriving the decimators and interpolators. The circuits are verified by SCNAP4 and HSPICE simulations.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
