Abstract
La incorporation into Hf-based gate dielectrics is a promising methodology for achieving low threshold voltage (Vth) metal/high-k n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) with the gate-first process. To clarify the impact of the Hf/La ratio in high-k dielectrics on device performance, we investigated high-k bulk and interface traps of polycrystalline silicon (poly-Si)/TiN/HfLaSiO/SiO2 stacks with various Hf/La ratios. We found that La incorporation is effective for improving electron mobility; however, in a pure LaSiO device, the mobility is degraded. Our charge-pumping (CP) measurements revealed that both high-k bulk traps and near-interface traps (Nit) near the conduction band, which cause mobility degradation, can be effectively passivated by La incorporation. These results imply that an optimized La ratio will lead to superior nMOSFET performance, while an appropriate Vth can be tuned.
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