Kinetics of defect creation in amorphous silicon thin film transistors

Abstract

We have developed a theoretical model to account for the kinetics of defect state creation in amorphous silicon thin film transistors, subjected to gate bias stress. The defect forming reaction is a transition with an exponential distribution of energy barriers. We show that a single-hop limit for these transitions can describe the defect creation kinetics well, provided the backward reaction and the charge states of the formed defects are properly taken into account. The model predicts a rate of defect creation given by (NBT)α(t/t0)(β−1), with the key result that α=3β. The time constant t0 is also found to depend on band-tail carrier density. Both results are in excellent agreement with experimental data. The t0 dependence means that comparing defect creation kinetics for different thin film transistors can only be done for the same value of band-tail carrier density. Normalization of bias stress data on different thin film transistors made at different band-tail densities is not possible.