Key Process Technologies for Stacked Double Si0.7Ge0.3 Channel Nanowires Fabrication

Abstract

In this study, key process technologies, such as epitaxy growth, fin structure etching, and selective etching of stacked Si/SiGe multilayer for the fabrication of double Si0.7Ge0.3 channel nanowires under a reasonable thermal budget are systematically investigated. A high crystal quality two-period Si0.7Ge0.3/Si stacked multilayer epitaxially grown with thin and distinct interfaces is first realized on a Si substrate. A vertical profile of the fin structure of Si0.7Ge0.3/Si stacked multilayer is achieved using HBr/O2/He plasma after fine-tuning the etching process. In addition, the highest tolerable temperature of 850 °C for the Si0.7Ge0.3/Si stacked multilayer under rapid thermal annealing is confirmed based on the crystal quality, Si0.7Ge0.3/Si interface, and Ge diffusion. Moreover, a rectangular Si0.7Ge0.3 extremity profile is realized by optimizing the concentration and temperature of tetramethyl ammonium hydroxide solution to achieve selective etching of Si to Si0.7Ge0.3 for Si0.7Ge0.3/Si stacked multilayers. Finally, a vertically stacked double Si0.7Ge0.3 nanowire structure is successfully prepared using these newly developed process technologies.