K‐band frequency doubler with low power consumption and compact size in 65 NM CMOS

Abstract

ABSTRACTIn this article, a K‐band frequency doubler with low power consumption and compact size using balanced topology is demonstrated. The circuit is fabricated using 65 nm CMOS technology and designed to operate from 23.2 to 26 GHz. The transformer based on the balun and the inductor is designed. Using a balun and inductor based on transformer, the circuit size is reduced and these achieve good balanced performance and input matching. The frequency doubler occupies and area of 0.6 × 0.29 and consumes a current of 5 mA from a 1 V supply. The fabricated frequency doubler exhibits a conversion gain of −8.4 dB at the input frequency of 12 GHz and an input power of 0 dBm. The suppression of the fundamental signal is 31.5 dB at input frequency of 12 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:93–95, 2017