Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

Abstract

Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG = 3 nm and 1 nm are explored for the first time by invoking HfxTi1-xO2 based high-k gate dielectric. The 3D device performance analysis is carried using self-consistent Poisson and Schrödinger equations based on a non-equilibrium Green’s function (NEGF) approach. The result analysis ensures the Si channel can be a continued option for future technology nodes as long as spacer dielectrics are driven with optimized techniques. The performance improvement in ultra-short length devices is carried by inducing single-k, dual-k, and hybrid spacers. The FinFET scaling using calibrated 3-D simulations reveals that the increased band gap due to the quantum confinement effect enables scaling to the sub 3 nm regime. At extremely scaled LG the device exhibits excellent electrical characteristics with subthreshold swing (SS) of ∼62 mV/dec, drain induced barrier lowering (DIBL) of 45.45 mV/V, switching (ION/IOFF) ratio of ∼108, high field effective electron mobility(µeff) of ∼108 cm2/(V-s) and maximum electron velocity of 5 × 108 cm/s. In addition, the performance impact of temperature, work function, device geometry, total gate capacitance (Cgg) and cut-off frequency (fT) are also determined with spacer dielectrics. This analysis and optimization ensure the experimental realization and will serve as a benchmark for future works. The result analysis also reveals that the scaling with Si for sub-3 nm regime is a viable option.