Junctionless Poly-Si Nanowire FET With Gated Raised S/D

Abstract

The short-channel effect (SCE) is an important issue in CMOS technology. In this paper, a junctionless (JL) poly-Si nanowire FET (NW-FET) with gated raised source/drain (S/D) was demonstrated to suppress the SCE. The gated raised S/D structure enhances the control of the channel by the gate. Therefore, a JL poly-Si NW-FET with the gated raised S/D exhibits reduced drain-induced barrier lowering and less channel length modulation effect. Additionally, when the gate bias exceeds the flat-band voltage, a JL poly-Si NW-FET with gated raised S/D exhibits a low parasitic S/D resistance owing to the formation of an accumulation layer in its S/D, which is useful for multi-gate-oxide applications. However, the gated raised S/D shows a high gate-induced drain leakage current in the off state. Therefore, the gate electrode of the gated raised S/D must be designed carefully to prevent high off current.