Joint Hybrid Frequent Value Cache and Multi-Coding for Data Bus Energy Saving

Abstract

In the deep submicron technology domain, the on-chip buses consume considerable amount of total energy of embedded multi-core chip. Lots of techniques have been produced to reduce the bus energy consumption. FVE (Frequent Value Encoding) and FV-MSB (Frequent Value-Most Significant Bit) which exploit abundant value locality on the data buses, are effective methods for reducing data bus energy consumption. In this paper, we propose a method that exploits more value locality that is overlooked by the FVE and FV-MSB. We found that a significant amount of non-frequent values and low-order bits of partial frequent values, not captured by the FVE and FV-MSB, produced large number of switching activity. Therefore, we produce an bus energy saving method based on frequent values and multi-coding which can be used to further reduce the on-chip data bus switching activity. The simulation results show that our method can reduce the ratio of switching activity by 18.7% on the data bus lines, and obtain the maximum ratio of energy saving by 17.76% and the average ratio about 16.91%, with 70nm technology when the coupling factor λ is 5. And the results also show that the method can still play a role when the technology size is further reduced in the future.