Joint Crosstalk Aware Burst Error Fault Tolerance Mechanism for Reliable on-Chip Communication

Abstract

In a Nano-scale technology, reliability is one of the main issues for on-chip communication systems. To make communication system more reliable, Joint Crosstalk Aware Multiple Error Correction with interleaving scheme is proposed for crosstalk errors. This technique is very useful while dealing with burst error. The number of burst errors which can be tolerated by this technique can be adjusted by changing the interleaving distance between adjacent bits of the same module. The burst of 9 adjacent errors can be corrected if 4 modules of encoder and decoder are used. The design is implemented on FPGA to calculate area overhead and delay. The proposed JMEC/JMEC-Inter encoder and decoder are both fast, with maximum operating frequencies of 163.308 MHz and 307.977 MHz respectively by trading off by I/O's pins (48.53 and 19.85 percent more I/O's than Hamming and JTEC respectively). The area consumed by the proposed technique is less than the 3 percent of the FPGA resources, making the technique good candidate on chip fault tolerance mechanism.