Abstract
This paper presents a new compact model, JFETIDG, for independent dual-gate JFETs. The model is applicable to JFETs with any combination of p-n junction or MOS gates, captures geometry and temperature dependencies. As a special case, it can model junctionless MOSFETs. The model is verified by comparison to experimental and TCAD data. Verilog-A code for the model is available in the public domain.
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Published version (
Free)
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
