Abstract

Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.

Highlights

  • Due to the rapid increase of data volume, the next-generation very high-throughput optical communication has attracted wide interest [1,2,3,4,5]

  • The evaluation using field programmable gate array (FPGA) proves that product codes with low-density parity-check (LDPC) codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput

  • Due to the suboptimal property of the iterative decoding algorithm and the intrinsic error-prone substructures in the LDPC structures, the error floor phenomenon exists when LDPC codes operate in the high signal-to-noise ratio (SNR) region [13,14,15]

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Summary

Introduction

Due to the rapid increase of data volume, the next-generation very high-throughput optical communication has attracted wide interest [1,2,3,4,5]. Due to the suboptimal property of the iterative decoding algorithm and the intrinsic error-prone substructures in the LDPC structures, the error floor phenomenon exists when LDPC codes operate in the high signal-to-noise ratio (SNR) region [13,14,15]. This phenomenon limits the application of LDPC codes for these high-throughput optical communications [13].

Residual Error Characteristics of Multiple Consecutive LDPC Codes
The Product Codes with LDPC Codes
Analysis of Residual Error Characteristics for Product Codes
Iterative Decoding of Product Codes
Performance of Product Codes Using Iterative Decoding
Hardware Evaluation for Iterative Decoding of Product Codes
Hardware Evaluation Platform
The Encoder Architecture
The Decoder Architecture
Experimental Results Based on Field Programmable Gate Array
Conclusions
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