Abstract
This paper reviews problems encountered in the 1 µm process development for 256K MOS RAM and forecasts submicron technology in the future. The 1 µm process consists of electron beam direct writing, dry etching, Mo-poly double gate and faulttolerant technologies. The major problems encountered are various process-induced defects caused by using electron beam direct writing, dry etching and thinner films. To realize an efficient submicron process, it is necessary to further reduce all the defects as well as to develop a device structure with high applicable voltage. The limiting device dimensions for MOS devices depend upon circuit form. The minimum dimensions are obtained for the CMOS form.
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