(Invited) Vlsi Carbon Nanotube Thin-Film Circuits

Abstract

With the availability of large quantities of electronically monodisperse carbon nanotubes (CNTs) [1], homogeneous semiconducting CNT thin films can be produced through a variety of solution-based methods including vacuum filtration [2], dielectrophoresis [3], evaporation-driven self-assembly [4], aerosol jet printing [5], and inkjet printing [6,7]. Through careful integration of these thin films with high-k gate dielectrics [8], CNT thin-film transistors (TFTs) can achieve device metrics that are competitive with polycrystalline silicon and amorphous oxide semiconductors [9]. Furthermore, with appropriate device geometries, doping schemes, and gate electrode materials, threshold voltage can be tuned to enable enhancement-mode p-type and n-type TFTs, resulting in CNT CMOS logic gates with subnanowatt static power dissipation and full rail-to-rail voltage swing [10]. While these results suggest that very-large-scale integration (VLSI) should be possible for CNT thin-film circuits, further improvements are needed in CNT TFT large-area spatial homogeneity and long-term environmental stability. Towards these ends, this talk will introduce encapsulation schemes and automated measurement strategies that yield wafer-scale CNT TFT arrays with sufficiently tight control over on/off ratio, subthreshold swing, and threshold voltage for VLSI CNT thin-film circuits. Using this methodology, large-area arrays of fully functional CNT TFT static random access memory (SRAM) cells are demonstrated with desirable static noise and write margins. [1] D. Jariwala, V. K. Sangwan, L. J. Lauhon, T. J. Marks, and M. C. Hersam, “Carbon nanomaterials for electronics, optoelectronics, photovoltaics, and sensing,” Chem. Soc. Rev., 42, 2824 (2013). [2] A. Behnam, V. K. Sangwan, X. Zhong, F. Lian, D. Estrada, D. Jariwala, A. J. Hoag, L. J. Lauhon, T. J. Marks, M. C. Hersam, and E. Pop, “High-field transport and thermal reliability of sorted carbon nanotube network devices,” ACS Nano, 7, 482 (2013). [3] M. Steiner, M. Engel, Y.-M. Lin, Y. Wu, K. Jenkins, D. B. Farmer, J. J. Humes, N. L. Yoder, J.-W. T. Seo, A. A. Green, M. C. Hersam, R. Krupke, and Ph. Avouris, “High-frequency performance of scaled carbon nanotube array field-effect transistors,” Appl. Phys. Lett., 101, 053123 (2012). [4] T. A. Shastry, J.-W. T. Seo, J. J. Lopez, H. N. Arnold, J. Z. Kelter, V. K. Sangwan, L. J. Lauhon, T. J. Marks, and M. C. Hersam, “Large-area, electronically monodisperse, aligned single-walled carbon nanotube thin films fabricated by evaporation-driven self-assembly,” Small, 9, 45 (2013). [5] M. Ha, J.-W. T. Seo, P. L. Prabhumirashi, W. Zhang, M. L. Geier, M. J. Renn, C. H. Kim, M. C. Hersam, and C. D. Frisbie, “Aerosol jet printed, low voltage, electrolyte-gated carbon nanotube ring oscillators with sub-5 µs stage delays,” Nano Lett., 13, 954 (2013). [6] B. Kim, S. Jang, M. L. Geier, P. L. Prabhumirashi, M. C. Hersam, and A. Dodabalapur, “High-speed, inkjet-printed carbon nanotube/zinc tin oxide hybrid complementary ring oscillators,” Nano Lett., 14, 3683 (2014). [7] B. Kim, S. Jang, M. L. Geier, P. L. Prabhumirashi, M. C. Hersam, and A. Dodabalapur, “Inkjet printed ambipolar transistors and inverters based on carbon nanotube/zinc tin oxide heterostructures,” Appl. Phys. Lett., 104, 062101 (2014). [8] Y.-G. Ha, K. Everaerts, M. C. Hersam, and T. J. Marks, “Hybrid gate dielectric materials for unconventional electronic circuitry,” Acc. Chem. Res., 47, 1019 (2014). [9] V. K. Sangwan, R. P. Ortiz, J. M. P. Alaboson, J. D. Emery, M. J. Bedzyk, L. J. Lauhon, T. J. Marks, and M. C. Hersam, “Fundamental performance limits of carbon nanotube thin-film transistors achieved using hybrid molecular dielectrics,” ACS Nano, 6, 7480 (2012). [10] M. L. Geier, P. L. Prabhumirashi, J. J. McMorrow, W. Xu, J.-W. T. Seo, K. Everaerts, C. H. Kim, T. J. Marks, and M. C. Hersam, “Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control,” Nano Lett., 13, 4810 (2013).