(Invited) The Scaling-Down and Performance Optimization of InAs Nanowire Field Effect Transistors

Abstract

Due to their fascinating properties, InAs nanowires have drawn great attention for the channel material in future transistors. Scaling-down has been an effective way to improve the performance of transistors continuously for decades. Here, we review our recent progresses on InAs nanowire field effect transistors (FETs) when they are scaled down. Our group investigates the electrical characteristics of InAs nanowire thinner than 10 nm. Both the size-effect and the contact properties of ultrathin nanowires are explored. Moreover, the effects of InAs crystal phase and orientation are studied for further optimizing the device performance. In addition, FETs with partial gate are studied to suppress the BTBT-induced off-current. Furthermore, to improve the electrostatics control of the gate, our group develops a method to fabricate vertical GAA FETs with all-metal electrodes based on self-catalyzed grown InAs nanowire arrays.