(Invited) Study of Minority Carrier Lifetime Killer by Synchrotron X-Ray Topography

Abstract

The lifetime of minority carrier is an important property of a semiconductor material that controls the performance of high voltage/ high power and frequency devices. For instance, in high power device applications, a longer carrier lifetime is desirable to mitigate power loss under forward bias. By comparison, a shorter lifetime is more suitable in high frequency devices as it help reduce power loss during switching cycles. Despite recent studies linking structural defects, growth parameters and material thickness to variation in carrier lifetime in silicon carbide epitaxial layers [1-3], little is known about these lifetime limiting defects/parameters and their influence on carrier recombination because of variability in measurement. Therefore, systematically identifying these factors will shed light into ways to mitigate/annihilate their effects. In this paper, we first report on the influence of structural defects on minority carrier lifetime in n-type 4H-SiC epitaxial layers. The lifetime maps for a 2” quarter wafer (sample 1) and a 4” diameter half wafer (sample 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the synchrotron X-ray topography (SXRT) map of structural defects. The lifetime map of sample 1 revealed a drastic reduction in carrier lifetime along the edges and inside one of its facets (facet 1), which was correlated with the presence of microcracks, BPD loops, overlapping triangular defects, high density of multi-layer Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). Like sample 1, sample 2 showed a reduced carrier lifetime along the edges, which corresponded to regions of high density of overlapping triangular defects, microcracks and BPD loops in the SXRT map. Furthermore, a shorter lifetime was observed in the middle region of sample 2. Synchrotron X-ray topography map correlated this shorter lifetime to networks of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that were generated during epilayers growth. Following further analysis of the SXRT maps, it was observed that the stacking faults in facet 1 of sample 1 were double Shockley stacking faults (DSSFs) that have likely nucleated from scratches present on the substrate surface and LAGBs present in that region, which propagated during epilayer growth. The mechanism of formation of these DSSFs is discussed in light of an electronic model proposed by Kuhr [4] and observed by Pirouz [5]. The mechanism of formation of the IDs and HLAs is also discussed. We discuss the mitigated influence of numerous morphological defects observed on the surface of both epilayer samples. Finally, the implication of these observations on the selection and processing of silicon carbide substrates for epilayer growth is addressed in light of the lifetime maps. 1. J. Hassan and J. P. Bergman, J. Appl. Phys. 105 (12), 2009 2. Louisa Lija, J. Hassan, I. Booker, P. Bergman and E. Janzen, Mat. Sci. Forum 740-742, 2013 3. B. Kallinger, P. Berwian, J. Friedrich, M. Rommel, M. Azizi, C. Hecht and P. Friedrichs, Mat. Sci. Forum 740-742, 2013 [4] P. Pirouz, et al., Phil. Mag. 86, 2006. [5] T. A. Kuhr et al., J. Appl. Phys. 92, 2002.