Abstract
Dislocation behavior during homo-epitaxy of 4H-SiC on offcut substrates by Chemical Vapor Deposition (CVD) has been studied using Synchrotron X-ray Topography and KOH etching. Studies carried out before and after epilayer growth have revealed that, in some cases, short, edge oriented segments of basal plane dislocation (BPD) inside the substrate can be drawn towards the interface producing screw oriented segments intersecting the growth surface. In other cases, BPD half-loops attached to the substrate surface are forced to glide into the epilayer producing similar screw oriented surface intersections. These screw segments subsequently produce interfacial dislocations (IDs) and half-loop arrays (HLAs). We also report on the formation of IDs and HLAs generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches. The HLAs are known to result in Shockley fault expansion within the epilayer which results in forward voltage drop and device failure.
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