(Invited) Strain Engineered Crack-Free GaN on Si for Integrated Vertical High Power GaN Devices with Si CMOS

Abstract

We demonstrated beyond 10 µm thick crack-free GaN growth on Si substrate using selective area growth technique. Systematic characterization by scanning electron and optical microscopy on the grown samples revealed that cracks nucleate and propagate on {1-1 00} planes in <1-2 10> directions. By developing {1 -101} facet planes in selective area growth, thermal mismatch strain relief at facet surfaces eliminate cracking and enable growth over 10 µm thick crack-free GaN on Si. These grown structures exhibited high crystalline quality throughout the thickness of the structure as validated by selective area diffraction in high resolution transmission electron microscopy, with a dislocation density of 2-3 x 108 cm-2 at the GaN surface. On the same Si substrate, we were able to fabricate enhancement mode CMOS devices. The overall progress reported here paves the way for monolithically integrated GaN technologies for RF and high power applications on Si CMOS devices.