(Invited) SiGe and III-V Materials and Devices: New HEMT and LED Elements in 0.18-Micron CMOS Process and Design

Abstract

The incorporation of new materials into CMOS scaling has become a necessity. Our previous work in SiGe and III-V integration shows promise in allowing further materials integration for increased transistor density. However, a principal concern is that investment returns by further increasing transistor density will likely be negative for all but possibly one or two corporations, and may be negative for all. Moore’s Law metrics for the benefits of incorporating III-V and other materials monolithically into silicon CMOS are not sufficient to determine innovative value for CMOS+X combinations. Such an environment that cannot use traditional metrics is a challenge for all organizations participating in the previous paradigm. Despite these challenging times, we list the likely characteristics of a new innovation path, and describe our efforts to follow it through research into ‘white space’ integrated circuits employing new materials and devices. Initially, we are designing novel integrated circuits, materials and processes incorporating GaN HEMTs, GaN and AlInGaP LEDs, and InGaAs HEMTs monolithically into existing silicon CMOS foundry processes. Both heteroepitaxy and wafer bonding are used in the process flow, and SiGe or Ge buffer layers are used in many processes. A modular process flow is incorporated so that the new devices can be modeled and incorporated into the design kit for a foundry process, allowing us to leverage much of the existing silicon design and manufacturing infrastructure. Our initial focus is on the demonstration of wafer-level integration of III-V devices with foundry 0.18 -micron CMOS devices on 200 mm wafers, and we report on the progress made in materials, device and circuit design towards this goal.