(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

Abstract

3D chip stacking approaches with TSV (thorough-silicon vias) are mainly classified into three categories: chip-to-chip, wafer-to-wafer, and chip-to-wafer 3D integration. The chip-to-chip technologies are widely used for traditional microelectronic packaging in which KGDs (known good dies) are assembled using one-by-one pick-and-place techniques. Although the assembly yield is high due to the use of KGDs, the assembly throughput is not sufficiently high, compared with wafer-to-wafer approaches. However, wafer-to-wafer technologies have a serious issue in total production yield that is exponentially decreased with the number of stacked layers because the failure dies cannot be removed from the wafers to be stacked. Therefore, chip-to-wafer 3D integration is thought to be a promising candidate to satisfy both the throughput and yield issues. However, chip-to-wafer 3D integration potentially has a trade-off between assembly throughput and alignment accuracies in the conventional robotic pick-and-place techniques. In order to address the problems, we have proposed and developed multichip-to-wafer 3D integration using liquid surface tension. From the technical point of view of chip-to-wafer bonding, we talk about the basic concept and recent studies of the self-assembly based 3D integration. These approaches using surface tension-driven multichip assembly are divided into two methodologies: one is non-transfer stacking without carrier wafers and the other one is transfer stacking with them. These carrier wafers are typically used for temporary wafer bonding in standard 3D integration processes. Here, we also introduce temporary multichip bonding technologies applicable to 3D integration with multichip transfer stacking in which an inorganic temporary adhesive and a debonding layer sensitive to near UV lasers are utilized. In this presentation, we introduce our multichip-to-wafer 3D integration studies with non-transfer and transfer stacking particularly focused on solder microbump bonding (indium/gold and tin/cupper), CVD (chemical vapor deposition)-oxide/CVD-oxide direct bonding, and hybrid bonding through a new material of Cu nano-pillars that have been most recently reported toward upcoming IoT (internet of things) and trillion sensor societies.