(Invited) Selective Epitaxial Growth (SEG) of Highly Doped Si:P on Source/Drain Areas of NMOS Devices Using Si3H8/PH3/Cl2 Chemistry

Abstract

In this paper we demonstrate the successful integration of in-situ doped Si:P epitaxially grown into the source/drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process employing a Si3H8/PH3/Cl2 based chemistry. A distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We report on material characterization results of the Si:P selective epitaxial growth (SEG). An optimized Si:P SEG process with a SEG rate of ~25 nm/min enables a 80-170s short deposition for typical epitaxial layers (35-70 nm), well suitable for high volume manufacturing (HVM). By integrating an isothermal in-situ removal of Si0.65Ge0.35 (protecting/covering the NMOS areas) with a high etch rate selectivity against the underlying thin SOI at process temperature allows to eliminate the in-situ H2 prebake and the cool-down to process temperature, significantly reducing recipe overhead and the need for a separated, dedicated pre-clean module.