(Invited) Investigation of Critical Interfaces in Few-Layer MoS2 Field Effect Transistors with High-k Dielectrics

Abstract

In this work, few-layer MoS2 FET-based devices were fabricated using top and bottom high-k dielectrics (Al2O3 and/or HfO2). Frequency-dependent C-V data of top-gate FETs shows dispersion in both the depletion and accumulation regions for the MoS2 devices signifying electrically active interface and possible border traps. Also, metal contact deposition conditions and sulfur treatments on MoS2 for source and drain determined that ultra high vacuum deposited metals were superior to those deposited only under high vacuum, and the sulfur treatment coupled with a forming gas anneal provides the lowest contact resistance (~2 kΩ·µm). With Al2O3 as the bottom-gate dielectric layer, a positive influence on HfO2 top-gate FET performance was achieved – even without any backside bias – because the top-gate intrinsic mobility and subthreshold slope were improved compared to SiO2 or HfO2 as back gate dielectric. Furthermore, a forming gas anneal is found to enhance device performance due to a reduction in charge trap density at dielectric interfacial regions, and improved metal contact formation.