(Invited) Investigation of Critical Interfaces in Few-Layer MoS2 Field Effect Transistors with High-k Dielectrics

Abstract

Transition metal dichalcogenides (TMDs) as 2D or few-layer semiconducting channel material are being widely studied to lower power consumption and obtain negligible short channel effects with continued transistor scaling [1-4]. Meanwhile, research needs to be conducted on top-gated, metal-oxide-semiconductor field effect transistors (MOSFETs) to correctly assess the possibility of TMDs supplanting silicon in the channel region. This is because top-gate device architectures face some key integration challenges that typical bottom-gate TMD FET structures do not experience. As an example, molybdenum disulfide (MoS2) is supposed to have no dangling interfacial bonds, making it difficult to form high-k dielectrics on them. Therefore, surface functionalization of TMDs has attracted attention [5-12]. However, detailed understanding on performance of transistors with metal/high-k/TMD top-gate stacks are still lacking. In addition, a major hurdle of incorporating these two-dimensional (2D) materials in device structures of any kind is the high contact resistance at the metal/TMD interface [13-15]. Recent results have shown that the backside dielectric can influence top-gate MOSFET performance [16]. In this work, few-layer MoS2 FET-based devices were fabricated using top and bottom high-k dielectrics (Al2O3 and/or HfO2). The C-V response of a top-gate, HfO2/MoS2 gate stack on a backside SiO2 layer demonstrated the existence of specific defects at the interface, which demonstrated frequency dependent “humps” in depletion – similar to conventional Si MOSFETs with unpassivated silicon dangling bonds in the dielectric/Si interfacial region. Also, a comparison of UHV and HV metal deposition on MoS2 as contacts for source and drain was done where results demonstrated that UHV deposited metals were superior to HV ones. In an additional experiment with Al2O3 as the bottom-gate dielectric layer, the intrinsic mobility and subthreshold slope were greatly improved compared to SiO2 or HfO2 as back gate dielectric FETs, indicating a positive influence on top-gate device performance even without any backside bias. Furthermore, a forming gas anneal is found to further enhance device performance due to a reduction in charge trap density at dielectric interfacial regions, and improved metal contact formation. Another significant finding in top-gate FET performance is the high-k dielectric screening effect of the backside Al2O3 layer. Results demonstrate that the extracted top-gate field effect mobility values are higher compared to SiO2 or HfO2 as a backside oxide – even though all FETs have the same top-side HfO2 dielectric oxide and no back bias. Acknowledgement – This work was supported in part by the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765, Science Foundation Ireland under the US-Ireland R&D Partnership Programme Grant Number SFI/13/US/I2862, and the center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA.