(Invited) Integration of III/V Hetero-Structures By Selective Area Growth on Si for Nano- and Optoelectronics

Abstract

The integrated circuit (IC) technology has seen an impressive development over the last decades due to the superior interface properties between Silicon (Si) and Silicon dioxide. The main driving force for the constant improvement in microchip performance was an aggressive reduction in transistor device size. Currently this miniaturization of planar devices has reached physical limits and new device architectures are introduced and investigated such as FinFET, Gate-all-around nanowire devices and TFET. A further boost in device performance is expected from the implementation of new channel materials with higher electron mobilities than Si such as Germanium (Ge) or III/V compound materials. In addition, due to the excellent optoelectronic properties of III/V materials, the monolithic integration of III/V based hetero-structures on Si is a very promising route to clearly enhance Silicon Photonics. In particular the cost-efficient integration of a light source on Si substrate is still missing to fully profit from Silicon Photonics. Selective area growth (SEG) of lattice mismatched materials on patterned Si wafers is a novel integration approach with obvious advantages: Since most III/V candidates of interest have a larger lattice constant than Si, misfit and threading dislocations are formed to release the strain. SEG in very narrow oxide trenches allows for a pronounced defect reduction. The high aspect ratio of the oxide sidewalls leads to an efficient defect trapping in the bottom part of the trench so that the top region has a high crystal quality (aspect ratio trapping (ART)). Because thick metamorphic buffer growth is not required to adjust the lattice constant and to achieve a low defect density, SEG is also very cost-efficient and has a better compatibility with common CMOS integration schemes. The successful application of ART has already been demonstrated for numerous material systems in group IV as well as for III/V compound materials and opens several routes for implementing new device integration concepts. In this presentation we show the monolithic growth of GaAs nano ridges by metal organic vapor phase epitaxy (MOVPE) on 300mm patterned Si wafers. The deposition in narrow trenches ensures a clear reduction in defect density whereas the growth out of the trench is manipulated in such a way, that III/V ridges with increased volume and various shapes can be realized. The huge advantage of these nano ridges is that they provide a free standing lattice constant which can serve as a buffer for different pseudomorphically grown III/V hetero-structures. For example the growth of compressively strained InGaAs/GaAs multi quantum wells (MQWs) on a GaAs ridge offers an interesting approach for the monolithic integration of a laser diode, since the III/V nano ridge can also act as a wave guide. The impact of the chosen MOVPE growth parameters on the observed ridge evolution is discussed in detail based on scanning electron microscopy (SEM), transmission electron microscopy (TEM) and X-ray diffraction reciprocal space maps (XRD-RSM). The advantages and potentials of different hetero-structures on patterned wafers are assessed in view of new nano device applications in optoelectronics.