(Invited) Innovation and Challenges of 3-D NAND Flash Technology

Abstract

NAND Flash has been improved by increasing the bit cost competitiveness and performance and enlarged its range of applications. Especially this cost reduction and performance improvement let the NAND Flash demand be increasing rapidly in the SSD applications. Needs of the market is demanding a high capacity and high speed of the NAND Flash for the information increase and exchange. Needs of these markets could be satisfied by implementation of a continuous scale down and multi bit. But 2D NAND Flash is not only faced with the difficulty of the scale down in a confined space, showing even marginal situations quality and performance secured in accordance with the scale down. 3D NAND Flash was able to break through the limit of the two-dimensional space by the vertical arrangement of cells in three-dimensional space. In this paper, we look at the critical technical elements for the vertical arrangement of 3D NAND Flash Cell and consider innovation and technology challenges of those elements. 3D NAND Flash meets the demand of the high density memory of the market by increasing the cell number per unit area with the increase of vertical stacks. This paper reviews the necessary stack number to meet the needs of the market and considers increasing the difficulty of the pattern formation increase with the high aspect ratio by increasing the stack height. . It also reviews some attempts to overcome the difficulty of the pattern formation for an effective bit cost reduction. 3D NAND Flash is there a big difference in electrical characteristics of 2D NAND Flash. First, we will compare the difference of the main characteristics of 3D NAND Flash and 2D NAND Flash. And we will look at the changes and challenges of the main electrical characteristics depending on the Stack increase for increased bit Cost reduction.