(Invited) III-V/Ge CMOS Device Technologies for High Performance Logic Applications

Abstract

One of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs . In order to realize III-V/Ge CMOS, common gate stack and S/D formation technologies are important. Here, an ALD Al2O3 gate insulator and Ta metal gate were used for common gate stacks for InGaAs and Ge. This is because ALD Al2O3 can provide good MOS interfaces with InGaAs as well as Ge with post ECR plasma oxidation. Also, self-align Ni-Ge and Ni-InGaAs, which can be formed simultaneously for InGaAs nMOSFETs and Ge pMOSFETs, were used as the metal source/drain (S/D) regions. By utilizing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance. We have found good transistor operation in both devices. High Ion/Ioff ratio of ~1e6 was obtained for InGaAs-OI nMOSFETs. The high electron and hole mobility of 1800 and 260 cm2/Vs and the mobility enhancement against Si of 3.5× and 2.3× have been demonstrated for InGaAs-OI nMOSFETs and Ge pMOSFETs, respectively.