Abstract

There have typically been two pinnacle goals in wafer bonding. The first and ongoing goal is to use wafer bonding methods to engineer starting materials; to integrate silicon with any other material to enable hetero-device architectures. The second aspiration is to continually shrink device footprints by bonding layer upon layer of devices vertically. Low temperature wafer bonding combined with advances in CMP (chemical mechanical polishing), temporary bonding, and advanced metrology characterization tools are enabling researchers to achieve these dreams come true. In particular, hybrid bonding, which enables simultaneous bonding of dielectric and metallic regions at the bond interface has produced extremely high performance devices and miniaturization of display technologies. This talk will highlight the various requirements for hybrid bonding and critical specifications for implementing complex bonding methods.

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