(Invited) Hybrid Bonding from Hype to Reality: How Will Hybrid Bonding Dtw Pave the Way to Large Set of Applications?

Abstract

Packaging and 3D integration have grown in importance as one of the key technology enablers to compensate for the slowing of two-dimensional scaling. Today, advanced 3D SoC are calling for fine interconnect where microbumps are hitting manufacturing limitation at 10µm pitch and beyond. Hybrid bonding technology is a good candidate for high interconnect density and connects dies in packages using tiny copper-to-copper connections, as opposed to bumps. This technology is already mature for wafer to wafer hybrid bonding and is expected to open new opportunities for die to wafer hybrid bonding, providing the same downscaling in pitch as well as additional flexibility and heterogeneity. This derived technology is of great interest for many applications such as chiplet, memory stacking, photonics with imagers, displays, optic transceivers and RF. However, there are still some hurdles to overcome to get this technology in full production. CEA-Leti has been involved in hybrid bonding process development for more than 20 years with industrial partners in wafer to wafer and today in die to wafer. This presentation will discuss about: Limitations of the technology: specific process challenges, interconnect alignment, design and architecture,...What needs to be developed to pass the hurdle: known good die, throughput & yield,...Key achievements / performances and roadmap at CEA-Leti on this promising technology