(Invited) High-Performance 2D Tellurium Transistors Towards CMOS Logic Applications

Abstract

The thirst for novel two-dimensional (2D) materials for ultra-scaled electronics keeps growing during the last decade as the downsizing trend of silicon-based conventional semiconductors is approaching its physical limit. An ideal paradigm of 2D materials suitable for logic device applications should possess high carrier mobility for both type of carriers, good air-stability, controllable doping scheme and a reasonable bandgap. Recently reported hydrothermal growth technique of 2D tellurium (Te) thin films, which meet all the above criteria, offers a new option for 2D material-based CMOS applications. Tellurium is a narrow bandgap p-type semiconductor (0.35 eV) with nearly symmetric mobilities for both electrons and holes of around 700 cm2/Vs at room temperature. It has one-dimensional chiral crystal structure and can be grown into 2D films under right conditions. Just like other 2D materials, these 2D facets of Te also contain no dangling bonds and therefore the 2D films can preserve the material properties and have great potential for miniaturizing device geometry in principle. Here we first report systematic investigation of 2D Te p-type transistor performance approaching atomic-thin limit. The device key parameters, such as field-effect mobility, on/off ratio and stability were thoroughly studied as a function of film thickness. The device performance was then optimized through contact and dielectric engineering, and large drive current over 1 A/mm was achieved. We further employed photo-current mapping method to show that rare accumulation-type ohmic contacts were formed using high work function metal (palladium). Finally, we present an atomic layer deposited (ALD) dielectric doping technique to effectively dope the intrinsically p-type channel into n-type with almost symmetric operations for both NMOS and PMOS. Prototypical inverters based on Te CMOS demonstrate great potential of constructing Te-based high-speed CMOS logic circuits. Our work not only established a comprehensive guideline for designing and optimizing 2D Te based CMOS devices, but also provided a device platform to explore versatility of 2D Te from many other perspectives, such as condensed matter physics and thermoelectronics.