(Invited) High-k Gate Dielectrics for Nanoscale CMOS Devices: Status, Challenges, and Future

Abstract

This paper describes historical efforts of replacing SiO2 by high-k dielectric, and an implementation of high-k/metal gate (HK/MG) gate stack into the product level of industry standard low power bulk technology and high performance silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) devices. HK/MG stack provides further device scaling in channel length and inversion thickness (Tinv), leading to enable contact gate pitch scaling. Mobility degradation with Tinv scaling and threshold voltage (Vt) variability due to random telegraph noise and random dopant fluctuations at 15nm node and beyond are discussed, followed by outlook of future generation CMOS devices.