Abstract
SiGe with practically whole Ge range (0-100%) becomes a common feature in many different device architectures explored nowadays. Both strained and relaxed layers are being considered in order to strain the active channel, reduce contact resistance or simply avoid certain technological obstacles. Modern pMOS transistors already utilize SiGe with Ge concentrations up to 50%. Use of such highly strained layers demands not only carefully optimized epitaxial processes but also sets stringed requirements to the whole device production flow. This paper deals with epitaxial deposition of SiGe with high Ge content, its properties and application in Source/Drain and channel of p-type fin-FETs.
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