(Invited) Graphene Synthesis and Transfer Improvements for Applications in the Semiconductor Industry

Abstract

A reliable CMOS compatible graphene integration route is still missing today. An overview of CVD graphene growth on Cu, Pt and Ge catalyst template wafers is given. Due to the high CVD graphene growth temperatures in combination with the necessity of a catalyst layer, a direct graphene growth on devices is unfeasible. As a result, a graphene transfer process to semiconductor devices is absolutely required. An overview of several graphene transfer approaches is given, starting with the standard wet etch based transfer. Next, a PVA based peeling transfer and the electrochemical bubble based transfer are described. Furthermore, the current transfer bottlenecks are identified. The paper ends with a discussion of the importance of using a passivation layer on the target wafer before transferring graphene and the implications of this passivation layer on the transfer process are outlined.