(Invited) Graphene Synthesis and Transfer Improvements for Applications in the Semiconductor Industry

Abstract

More than 10 years have passed since A. Geim and K. Novoselov published their ground breaking papers that triggered the worldwide 2D material research. Currently, the first graphene products are being commercialized (e.g. graphene inks, graphene reinforced nanocomposites), but the graphene market is still in its infancy. Graphene has the potential to become an important material in the semiconductor industry due to its outstanding properties (e.g. high mobility, transparency, gapless character which makes it to absorb light from the UV up to the THz spectral regimes, etc.). These characteristics make the material an ideal candidate for use in high-end applications (e.g. photonic modulators and detectors, graphene based interconnects...). For example, graphene detectors could have a bandwidth well above 200 GHz, which makes them outperforming current Ge based devices for optical communications. One of the bottlenecks that need to be overcome is the reliable integration of 2D materials in an advanced CMOS production environment. Chemical vapor deposition (CVD) is the most mature technique for the production of high quality graphene, but the majority of the graphene synthesis work is still performed on foils or single crystals. In order to reliably scale the production of graphene, a wafer scale growth is likely unavoidable. Such a wafer scale growth poses additional boundaries on the production of graphene due to the limited stability of thin films (e.g. dewetting and diffusion phenomena) at the high graphene growth temperature. These effects make the recycling of expensive graphene growth template wafers very challenging. An overview will be given of wafer scale graphene growth on Cu, Pt and Ge thin film surfaces. The pros and cons of the different graphene growth templates will be outlined. Platinum remains an interesting material for CVD graphene growth, since it is an excellent catalytic material for the growth of high quality monolayer graphene and millimeter sized graphene islands. Furthermore, a growth-etch-regrowth CVD technique can be used to minimize defect sites and the edge orientation of graphene grains can be controlled using this growth-etch technique. The subsequent step of a reliable integration of graphene is its transfer to a target wafer. Since optimized CVD growth processes of graphene are typically done at high temperatures (> 400 °C) on top of a catalyst layer, the development of a transfer process is crucial. This transfer step remains the most important bottleneck for the fabrication of reliable graphene based devices. Several graphene release and bonding procedures have been proposed in literature based on different mechanisms including etching of the substrate or catalyst layer, bubble based transfer methods (i.e. electrochemistry based, ultrasound based and bubble formation as a result of a chemical reaction), peeling methods, and wedging based transfer. Also, the majority of the transfer methods rely on an intermediate support layer, apart from a few exceptions. However, these support-free transfer methods still rely on etching of the catalyst layer, which results in metal contamination and avoids the reuse of the catalyst template. Typical problems associated with state-of-the-art 2D material transfers include polymer residues and metal contamination, additional wrinkle formation caused by a wet transfer, macroscopic cracks caused by handling of the 2D material, presence of interfacial water or solvents between the target wafer and graphene, graphene delamination issues during or after transfer, etc. An overview of the different transfer possibilities and challenges will be given, and a road towards a CMOS compatible transfer will be proposed. It is shown that control over interfacial water between graphene and its growth and target substrate is key to achieve a reliable graphene transfer process. Figure 1